Enhanced FPGA image processing development environment
7 Mar 2017
VisualApplets 3.0 is a 64-bit version of the hardware programming tool for FPGA processors and features extension packets and new functions. This new version includes additional operator libraries (Extension Libraries), which provide an expanded range of functions through licensed extensions. The first of these extensions are for segmentation, classification and compression. More will be released in the future for further individual image processing applications and embedded vision solutions.
The VisualApplets development environment allows hardware, software and application engineers to use FPGA processors for their image processing needs. It simplifies the development of image processing routines as no knowledge is required of circuitry, synchronisation, timings or FPGA programming.
The new version contains operators to represent loops in the data flow model, allowing image sequences and comparisons, as well as image batch processing for applications such as rolling average to be calculated with a highly effective use of resources on the FPGA. This further enhances the possibility of using a frame grabber or camera equipped with an FPGA as a high performance image processor.
In addition, the Fast Fourier Transformation FFT operator has been expanded to efficiently implement more complex filters, such as band pass filters, that have a high computing load. FFT is used in a wide range of applications, such as image analysis, image filtering, image reconstruction and image compression.
Silicon Software GmbH was founded in 1997 as a product development and manufacturing company with focus on the automation and machine vision markets. Headquarters are located in Mannheim, Germany where Silicon Software develops and produces off-the-shelf and customised OEM hardware and software solutions.
- Quick and easy development of hardware designs
- Hardware applets can be used immediately with microDisplay and the SDK
- No knowledge of circuitry, synchronization, timings or FPGA programming is required